1. Field of the Invention
This invention relates to a semiconductor device.
2. Description of Related Art
There has been principally used a silicon oxide film as a gate insulating film in semiconductor devices having planar transistors. However, as the configuration of semiconductor devices has been more and more miniaturized and integrated, and silicon oxide films serving as gate insulating films have been made thinner, leak current has increased to a non-negligible level. Therefore, attempts have been made to use a high-k (high dielectric-constant) film with a high relative dielectric constant in a gate insulating film.
Japanese Patent Application Publication No. 2011-14689 (Patent Document 1) discloses a planar transistor which is designed to realize a large work function by segregating halogens on an interface between a gate insulating film including a high-k film formed on a semiconductor substrate and a metal gate film formed on the gate insulating film.
Japanese Patent Application Publication No. 2011-49282 (Patent Document 2) discloses a technique for forming a high-performance and low-voltage metal-insulator-semiconductor field effect transistor (MISFE) by using a damascene process to form a gate insulating film including a high-k film and a metal gate film without exposing the gate insulating film and the metal gate film to annealing for activation of source and drain regions.
On the other hand, the short channel effect of planar transistors has become more noticeable as the configuration of semiconductor devices is miniaturized as described above. In order to prevent reduction of threshold voltage possibly caused by this short channel effect, an embedded gate transistor has been proposed, in which a gate insulating film is formed on the inner walls of a trench for gate electrode formed in the surface of a semiconductor substrate, and a gate electrode is embedded in the trench surrounded by the gate insulating film.
Japanese Patent Application Publication No. 2005-142203 (Patent Document 3) discloses an embedded gate transistor which is designed to suppress reduction of effective electric field and increase of threshold voltage by forming a gate insulating film on inner walls of a trench for gate electrode such that the gate insulating film has a smaller thickness at the corners of the trench bottom at least than the thickness of the film on the side walls of the trench.
As described above, there are known various techniques to cope with miniaturization and integration of semiconductor devices.
In some semiconductor devices such as a DRAM (Dynamic Random Access Memory), an embedded gate transistor is used in a memory cell region while a planar transistor having a gate insulating film including a high-k film is used in a peripheral transistor region.
The inventors of this invention have reviewed a DRAM having the aforementioned configuration and the manufacturing method thereof, and results obtained will be described with reference to FIGS. 18 to 29.
As shown in FIG. 18, a DRAM (semiconductor device) 300 has a memory cell region 300a and a peripheral transistor region 300b. The memory cell region 300a and the peripheral transistor region 300b are divided into a plurality of active regions 11a, 11b, 11c by STIs (Shallow Trench Isolations) 12 formed in a semiconductor substrate 10. There are formed, in the active region 11a of the memory cell region 300a, embedded gate transistors for memory cells. There are respectively formed, in the active regions 11b and 11c of the peripheral transistor region 300b, n-channel and p-channel planar transistors (hereafter, referred to as the peripheral transistors) each having a gate insulating film including a high-k film.
A manufacturing method of the DRAM 300 will be described with reference to FIGS. 19 to 29.
Firstly, as shown in FIG. 19, STIs 12 for defining the active regions 11a, 11b, and 11c are formed in a semiconductor substrate 10 formed of a p-type silicon substrate. Then, an insulating film 16 is formed to cover the top faces of the STIs 12 and the semiconductor substrate 10
As shown in FIG. 20, embedded gate transistors are formed in the active region 11a of the memory cell region 300a. Each of the embedded gate transistors for memory cells has a gate insulating film 18, a gate electrode 20, an insulating film 23, and impurity diffusion regions 14a, 14b. 
Subsequently, as shown in FIG. 21, a silicon oxide film 26′ is formed on the structure shown in FIG. 20. As shown in FIG. 22, the silicon oxide film 26′ on the peripheral transistor region 300b is removed, whereby a first interlayer insulating film 26 is formed in the memory cell region 300a. 
Next, as shown in FIG. 23, a high-k film 28′ is formed to cover the first interlayer insulating film 26 and the insulating film 16 in the peripheral transistor region 300b. 
After that, a metal film and a doped polysilicon film are sequentially stacked on the structure shown in FIG. 23, and the stacked films are patterned. Thus, as shown in FIGS. 24 and 25, a metal gate film 30 and an upper gate film 32 are formed in each of the active regions 11b, 11c of the peripheral transistor region 300b. The height from the semiconductor substrate 10 to the top face of the metal gate film 30 sometimes becomes higher than the height from the semiconductor substrate 10 to the top face of the first interlayer insulating film 26. Further, as shown in FIG. 25, the height b of the top face of the upper gate film 32 sometimes becomes higher than the height A of the top face of the first interlayer insulating film 26.
Next, the high-k film 28′ in the memory cell region 300a and the peripheral transistor region 300b except the one under the metal gate film 30 are removed. As a result, as shown in FIG. 26, a gate insulating film 28 including a high-k film is formed in each of the active regions 11b, 11c of the peripheral transistor region 300b. 
Next, as shown in FIG. 27, bit contact holes 27 are formed in the first interlayer insulating film 26. Subsequently, as shown in FIG. 28, a first interlayer insulating film 26 is formed to fill the bit contact holes 27 while a fifth conductor film 39 is formed to cover the upper gate film 32.
Subsequently, a sixth conductor film 43 is stacked on the fifth conductor film 39. When the height of the top face of the upper gate film 32 is higher than the height of the top face of the first interlayer insulating film 26, there is generated a difference in level between the top face of the fifth conductor film 39 and the top face of the sixth conductor film 43.
After that, as shown in FIG. 29, CMP (Chemical Mechanical Polishing) or etching is performed so that a contact plug 42 formed of a first conductor film obtained by processing the fifth conductor film 39 and a second conductor film 45 obtained by processing the sixth conductor film 43 are formed in the memory cell region 300a. The second conductor film 45 constitutes a bit line. Gate electrode stacks 49 are formed on the gate insulating film 28 in the peripheral transistor region 300b. Each of the gate electrode stacks 49 has a metal gate film 30, an upper gate film 32, a fourth conductor film 40 obtained by processing the fifth conductor film 39, and a third conductor film 44 obtained by processing the sixth conductor film 43.
Subsequently, low concentration impurity diffusion regions 46n, 46p and high concentration impurity diffusion regions 48n, 48p are formed in the semiconductor substrate 10 at the widthwise opposite ends of the gate electrode stack 49.
Subsequently, according to the same procedures as a conventional semiconductor device manufacturing method, as shown in FIG. 18, an insulating film 55, capacitors 54 in the memory cell region 300a, contact plugs 50 in the peripheral transistor region 300b, upper wirings 51, 53, via plugs 52 and the like are formed to complete a DRAM 300.